The present invention concerns a digital circuit which utilizes a phase locked loop to control off-chip to on-chip clock skew.
Within an integrated circuit, delay introduced by capacitance within logic components on the integrated circuit can cause clock skew between a clock signal coming in from off the integrated circuit (off-chip clock) and the clock signal used within the integrated circuit (on-chip clock).
In the prior art, phase locked loop circuits have been used to control off-chip to on-chip clock skew. However, these prior art circuits generally incorporate custom analog circuitry which makes these circuits unsuitable for use in a gate array that provides only digital circuitry. Further, the prior art circuits generally introduce jitter into the clock signal which, although usually acceptable, is not desirable. Also, many of the prior art designs require the use of external components which, while being acceptable, is also not desirable.
For examples of prior art phase locked loop systems, see M. Johnson, et al., A Variable Delay Line PLL for CPU-Compressor Synchronization, IEEE Journal of Solid State Circuits, Vol. 23, No. 5, October 1988, p. 1218; D. Jeong et al., Design of PLL-Based Clock Generation Circuits, IEEE Journal of Solid State Circuits, Vol. 22, No. 2, April 1987, p. 255; and K. Kohiyama, et al., A Single-Chip Digital PLL System for TV Image Processing, ISSCC DIGEST OF TECHNICAL PAPERS, Session 15, Video Signal Processors, Paper FP 15.1, February, 1991, p. 248.